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Hardware Engineer

Barefoot Networks is a team of visionaries, experienced technologists and engineers who have created a blueprint for designing and operating the world’s fastest and most programmable networks.  Our team is driven by deep engineering skills and a love of cutting-edge projects.  We are building the world’s fastest switches that are also fully programmable, ensuring the network can adapt to meet the emerging needs of applications and empower users to write solutions rapidly, and to innovate broadly.  We believe that when the network is fully programmable—that is, both the control plane and data plane are under the control of the end user— the networking industry will enjoy the same innovative explosion as we have seen in software.

Programmable data planes enable a whole new ecosystem of advanced networking applications, and the field of possibility is mind-bogglingly wide. It ranges from advanced network monitoring, analysis, and diagnostics, to building a large-scale data analysis platform, to embedding some middle-box functions in switches/routers, and to jointly designing a network and the apps running on the network. At the core of this revolution are the technologies that Barefoot is building: languages, compilers, and tools co-designed with fully programmable hardware. We're just starting to scratch the surface of this novel and exciting area, and we're looking for passionate engineers who can join this amazing journey with us!


Primary Responsibilities:

  • Implement synthesis implementation flows and able to debug and provide solution tailoring various synthesis issues such as hierarchical synthesis, clock gating, etc. 
  • Implementing Static Timing Analysis flow and drive timing closure at chip/cluster level
  • Drive power estimation at RTL and gate level implementation and do roll-ups to for static and dynamic power closure
  • Drive method to implement logical ECOs using tools like conformal LEC 
  • Interface with RTL design team to implement efficient power-saving techniques 
  • Interface with physical design, DFT team to address triage and debug of timing paths, manage constraints 



  • Ideal candidate holds MS in Electrical/Computer Engineering with 6+ years of relevant experience working in CAD, Static Timing Analysis. 
  • Hands on experience of synthesis using Design Compiler or Genus Compiler. 
  • Experience in logic synthesis and equivalence checking flow such as Conformal LEC, Conformal ECO required
  •  Experience with power estimation to determine static and dynamic power at gate level with vector-less and vector-based flows
  • Expertise and in-depth knowledge of industry standard EDA tools such as PrimeTime, Tempus, Joules, PTPX 
  •  Proficient in scripting languages such as Perl, Tcl, Python

What We Offer

  • Work in the Silicon Valley with legendary pioneers
  • Work with exceptionally passionate, talented and inspiring colleagues
  • High-energy atmosphere of a bold, young company disrupting the networking industry
  • Competitive compensation package with strong benefits plan and equity
  • Lots of freedom for creativity and personal growth
  • Excellent opportunity to be a part of ground-breaking innovation and make a lasting impact!


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